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MCU
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Product Description
AEC-Q100 Qualified
ASIL-B Safety Level Compliant
ARM Cortex-M0+ Core
Configurable Nested Vector Interrupt Controller (NVIC)
Single-cycle I/O access: 50% faster than standard I/O, improves external event response speed, supports bit manipulation and software protocol simulation
Two-stage pipeline: reduces cycles per instruction (CPI), accelerates branch instructions and interrupt service routine (ISR) entry, reduces power consumption
Superior code density to 8/16-bit MCUs: reduces Flash usage, system cost, and power consumption
100% compatible with ARM Cortex-M0 and some ARM Cortex-M3/M4: allows reuse of existing compilers and debugging tools
Simplified architecture: 56 instructions and 17 registers, facilitating programming and efficient handling of 8/16/32-bit data storage
Linear 4GB address space: no paging/segmentation, reducing software complexity
Supports ARM third-party ecosystem: provides software and hardware tools to shorten development time/cost
Supports Systick timer: with 8-bit prescaler and enable function
4 DMA channels, supporting up to 41 peripheral hardware trigger sources
DIVSQRT module: supports 32-bit integer division and square root operations
Memory
Up to 128 KB of ECC-enabled program flash (PFlash)
Up to 16 KB of ECC-enabled SRAM
Single-power supply (2.7-5.5 V), supports complete flash programming/erasing/reading operations
Clock System
Fast internal RC oscillator (FIRC), up to 48 MHz
Fast crystal oscillator (FXOSC), range 4-40 MHz
Slow internal RC oscillator (SIRC), up to 2 MHz
Slow crystal oscillator (SXOSC), 32.768 KHz
Low-power oscillator (LPO), 750 Hz
Keywords:
MCU
AEC-Q100 Qualified
ASIL-B Safety Level Compliant
ARM Cortex-M0+ Core
Configurable Nested Vector Interrupt Controller (NVIC)
Single-cycle I/O access: 50% faster than standard I/O, improves external event response speed, supports bit manipulation and software protocol simulation
Two-stage pipeline: reduces cycles per instruction (CPI), accelerates branch instructions and interrupt service routine (ISR) entry, reduces power consumption
Superior code density to 8/16-bit MCUs: reduces Flash usage, system cost, and power consumption
100% compatible with ARM Cortex-M0 and some ARM Cortex-M3/M4: allows reuse of existing compilers and debugging tools
Simplified architecture: 56 instructions and 17 registers, facilitating programming and efficient handling of 8/16/32-bit data storage
Linear 4GB address space: no paging/segmentation, reducing software complexity
Supports ARM third-party ecosystem: provides software and hardware tools to shorten development time/cost
Supports Systick timer: with 8-bit prescaler and enable function
4 DMA channels, supporting up to 41 peripheral hardware trigger sources
DIVSQRT module: supports 32-bit integer division and square root operations
Memory
Up to 128 KB of ECC-enabled program flash (PFlash)
Up to 16 KB of ECC-enabled SRAM
Single-power supply (2.7-5.5 V), supports complete flash programming/erasing/reading operations
Clock System
Fast internal RC oscillator (FIRC), up to 48 MHz
Fast crystal oscillator (FXOSC), range 4-40 MHz
Slow internal RC oscillator (SIRC), up to 2 MHz
Slow crystal oscillator (SXOSC), 32.768 KHz
Low-power oscillator (LPO), 750 Hz
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